A semiconductor crosspoint memory array circuit is exemplified by a row-column array of binary memory storage cells, that is, a two-dimensional array of such cells integrated in a single semiconductor body (chip), a separate one of such cells located at each crosspoint (intersection) of a row word access line and a column bit access line. Each cell can store a single bit of data, denoted by the conventional binary 1 or 0. For definiteness, assume that the number of row word access lines (wordlines) is n and that the number of bit access lines is m, so that there are n words stored in the array, each word containing m bits. The data stored in all cells on a given wordline forms a string of m bits, composed of the stored binary 1's and 0's, which can be viewed as a complete binary word stored in those cells. The bit stored in each such cell on the given wordline can then be read out by activating the given wordline and detecting the voltage level on each column bit line--a high voltage level corresponding to a stored binary 1, and a low voltage level corresponding to a stored binary 0. Thus the entire word consisting of the string of m bits stored on the given wordline can be read out by activating that wordline and detecting the voltage level on each bit line.
In a semiconductor random access memory (RAM), new data can be written into any cell by activating the wordline on which the cell is located and supplying a suitable voltage (high voltage for storing 1, low voltage for storing 0) to the bit line on which the cell is located. In an integrated circuit, each memory storage cell typically comprises a transistor in series with a storage capacitor, whereby the array of such cells forms a dynamic random access memory (DRAM) array, each cell thus storing either a quantity of charge to represent a stored binary 1 or no charge to represent a stored binary 0. Because of leaking of stored charge from a dynamic memory cell, a refresh operation for regenerating the stored data is perfomed by a separate refresh cycle for each stored word, involving activating the corresponding wordline, sensing and amplifying the corresponding stored charge, and thereby restoring the desired stored charge in all cells of the word. Typically, during a refresh operation, each of the wordlines is activated in sequence, one after the other, until all wordlines have been activated and hence all stored words have been refreshed. Alternatively, each cell can be a flip-flop arrangement of transistors, whereby the array of such cells forms a static random access memory (SRAM) array with no need for any refresh operation.
In many practical applications, it is desired to read out those and only those stored words having a specified portion thereof that matches a test word portion, such test word portion being a string of bits ordinarily containing fewer than m bits. Each of the stored words is called a "record"; the totality of such records forms a "file". For example, consider a memory array for storing a mailing list in which each (complete) stored record has m=512 bits representing in a specified sequence the name, post-office address, and age of a different person. Each such name is stored in a first predetermined portion ("name field") of the record; each such post-office address, in a second predetermined portion ("post-office address field"); and each such age, in a third predetermined portion ("age field"). It is often desired to read out of the mailing list the names and post-office addresses (as well as ages) of all persons having their ages equal to a prescribed value, say 32 (in the decimal system of numbers). A "content addressable" memory arrangement enables such a read out. That is, those and only those (complete) stored records are read out, each of whose respective portion corresponding to age of the person ("age field") matches the binary equivalent of (the prescribed age) decimal 32. Thus, the record of every person of age 32 is selected for read out, and no others. The age portion of each (complete) stored record will be called the "unmasked" portion; the remaining name and post-office address prtion ("name and address field") will be called the "masked" portion. The unmasked portion of each record is sometimes called the " associating field"; the masked portion, the "associated field". Thus, the test word portion is effective to associate the entire contents of every record (name, post-office address, 32) which has a corresponding portion thereof that matches the test word portion. Hence the term "content addressable" or "associative" memory is used to denote such a memory arrangement. It may also be desired to read out of the mailing list the name and post-office address of only one of the many persons of age 32. Again, a content addressable or associative memory can perform such a read out function.
The test word portion itself generally is thus a string containing less than m bits. It can thus be viewed as an incomplete word formed from a complete word (sometimes called the "comparand" or "search argument") having a portion thereof masked by a "masking word", whereby the remaining (unmasked) portion of the comparand forms the test word portion. During content addressing, it is this test word portion that determines which of the records are selected for (associative) read out. The entire masking word itself is composed of a string of m bits, a "1" representing a masking of, and a "0" representing an unmasking of, the corresponding bits in the comparand. (Thus, in the example of the mailing list, the masking word would contain solely 0's in the age field and solely 1's in the remaining name and post-office address fields.) Only the resulting complementary (unmasked) portion of the comparand will then be effective to perform the desired memory content addressing or association function. Thus, those bits in the comparand which are located at bit positions that are masked by the masking word behave as "don't cares"--i.e., do not influence the content addressing process of selecting records for read out.
Usually, as a matter of convenience, the masking word is implemented through its complement, the unmasking word, which is composed of only one (or at most a few) contiguous string(s) of unmasking bits--i.e., binary 1's located at a number of successive contiguous bit positions, and binary 0's located at all the remaining bit positions. In general, however, the unmasking word and hence the unmasked portion of the comparand can be composed of bits that are scattered in any desired way among the various bit positions corresponding to the comparand. Thus, each binary 1 in this unmasking word corrsponds to binary 0 in the masking word and is therefore effective to select a corresponding bit of the test word portion of the comparand, while all the binary 0's in the unmasking word behave as the "don't cares" with respect to the comparand.
In a paper by R. M. Lea entitled "The Comparative Cost of Associative Memory," published in The Radio and Electronic Engineer, Vol. 46, (1976) pp. 487-496, at pp. 490-491, an integrated circuit memory array of content addressable memory cells is disclosed. In the circuit, all words that are stored in the cells of the memory array can be simultaneously tested to locate those words whose unmasked portions match the test word. That is, a "word-parallel" search of the entire array can be performed. Each cell in the array comprises a dynamic memory element with four transistors per cell, instead of the more conventional and simple dynamic memory cell comprising a capacitor accessed by a transistor (which is not content addressable). However, the requirement in that circuit for four transistors per cell, as well as an additional requirement of multiple voltage power supplies, causes it to be unduly expensive in terms of cost and size per cell, whereby the total storage capacity of the memory array--i.e., the number of storage cells (and hence records) that can fit on a single semiconductor chip--is undesirably limited.